Description: Loop Tiling for Parallelism, Hardcover by Xue, Jingling, ISBN 0792379330, ISBN-13 9780792379331, Brand New, Free shipping in the US For researchers and practitioners involved in optimizing compilers, and students in advanced computer architecture, Xue (computer science and engineering, U. of New South Wales, Australia) explores the use of one of the most important compiler optimizations as it is used with parallel machines. He shows how it can reduce communications cost and improve parallelism for distributed memory machines. After providing mathematical foundations, he investigates loop permutability in the framework of non-singular loop transformations, discusses the necessary machineries required, and presents current results for finding tiling choices with the minimal communication and time. Each chapter includes references to the original literature. Annotation c. Book News, Inc., Portland, OR ()
Price: 188.11 USD
Location: Jessup, Maryland
End Time: 2024-12-01T05:13:40.000Z
Shipping Cost: 0 USD
Product Images
Item Specifics
Return shipping will be paid by: Buyer
All returns accepted: Returns Accepted
Item must be returned within: 14 Days
Refund will be given as: Money Back
Return policy details:
Book Title: Loop Tiling for Parallelism
Number of Pages: Xix, 256 Pages
Publication Name: Loop Tiling for Parallelism
Language: English
Publisher: Springer
Subject: Systems Architecture / Distributed Systems & Computing, Systems Architecture / General, Computer Science
Publication Year: 2000
Type: Textbook
Item Weight: 44.4 Oz
Subject Area: Computers
Item Length: 9.3 in
Author: Jingling Xue
Series: The Springer International Series in Engineering and Computer Science Ser.
Item Width: 6.1 in
Format: Hardcover
